The escalating requirements for high density and performance associated with ultra large scale integration semiconductor devices require design rules of 0.18 micron and under, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.18 micron and under challenges the limitations of conventional interconnection technology.
Conventional subtractive etching methodology comprises forming a first inter-layer dielectric on a semiconductor substrate, typically monocrystalline silicon, with conductive contacts formed therein for electrical connection with an active region on the semiconductor substrate, such as a source/drain region. A metal layer, such as aluminum or an aluminum alloy, is deposited on the first inter-layer dielectric, and a photoresist mask is formed on the metal layer to define a desired conductive pattern. The metal layer is then etched through the photoresist mask to form the conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spacings therebetween. A dielectric layer is then applied to the resulting conductive pattern to fill in the gaps and the surface is planarized, as by conventional etching or chemical-mechanical polishing (CMP) planarization techniques.
A through-hole is typically formed in an overlying inter-layer dielectric to expose an underlying metal feature for interconnection. In U.S. patent application Ser. No. 08/924,133 filed on Sep. 5, 1997, now U.S. Pat. No. 6,046,106 issued Apr. 4, 2000, a high density plasma (HDP) oxide is employed as a gap filling material to achieve superior conformal coverage vis-a-vis SOG and conventional oxides deposited by plasma enhanced chemical vapor deposition. HDP oxides also exhibit higher density than SOG, greater chemical stability, and greater etch resistance. The entire disclosure of U.S. patent application Ser. No. 08/924,133 is incorporated herein by reference.
As shown in FIGS. 1 and 2, conventional practices comprise depositing metal layer 11 on interlayer dielectric 10, which is typically formed on a semiconductor substrate containing an active region with transistors (not shown). After photolithography, etching is conducted to form a patterned metal layer comprising metal features 11a, 11b, 11c and 11d with gaps therebetween. A dielectric material 12, such as spin on glass (SOG), is typically deposited to fill in the gaps between the metal features, and baked at a temperature of about 300.degree. C. to about 450.degree. C., for a period of time up to about two hours, depending upon the particular SOG material employed. At a design rule of about 0.18 micron, metal lines shrink to a width of about 0.25 micron and interwiring spacings shrink to a width of about 0.3 micron. At such reduced dimensions, it is extremely difficult to satisfactorily fill in the interwiring spacings voidlessly and obtain adequate step coverage to form a reliable interconnection structure.
Conventional metal features comprise a composite layer comprising, for example, a lower metal barrier layer, such as titanium (Ti), an intermediate or primary conductive layer, e.g. aluminum or an aluminum alloy, and an anti-reflective coating (ARC) thereon, such as titanium nitride(TiN). Such a composite metal line is conventionally patterned into a plurality of metal features, e.g. conductive lines, employing anisotropic etching, typically with fluorine and/or chlorine chemistry. Subsequent to etching, a wet cleaning procedure is conducted in an attempt to remove etching residue. Such conventional wet cleaning typically comprises treatment with a solvent. Subsequent to cleaning, the gap filling dielectric layer is deposited to fill the gap between the metal features.
In conducting such conventional procedures, particularly as the design rule is scaled down to 0.18 micron and under, it is extremely difficult to effectively remove etching residues formed during patterning. Such etching residues are believed to attack the side surfaces of metal features and form voids. For example, ammonia from the cleaning solution can combine with residual chlorine from the etching process to form hydrochloric acid which attacks the side surfaces of the metal feature. Such corrosion of the side surfaces also results in voiding upon gap filling, thereby significantly increasing electromigration and, hence, significantly limiting the lifetime of the metal line as well as degrading device performance.
Electromigration in a metal interconnection line can be characterized by the movement of ions induced by a high electrical current density. Miniaturization demands long interconnects having small contacts and small cross-sections. Such reduced feature sizes are characterized by high electrical current density and, consequently, increased metalization electromigration failures. The increased susceptibility to electromigration as design features shrink is exacerbated by the corrosion of side surfaces of metal lines by etching residues and the formation of voids.
There exists a need for interconnect methodology enabling the formation of patterned metal lines without residues on side surfaces of the metal lines and without the generation of voids. There exists a particular need for interconnect methodology enabling gap filling patterned metal lines in semiconductor devices having a design rule of about 0.18 micron and under without an attendant decrease in electromigration resistance.